Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device comprising: an underlayer interconnect layer; an interlayer dielectric film formed with a connection hole reaching the underlayer interconnect layer; and an upper interconnect layer buried in the connection hole, wherein the interlayer dielectric film includes an insulating film containing an impurity for detecting a first etching end point, a first insulating film, an insulating film containing an impurity for detecting a second etching end point and a second insulating film, these four films being laminated in this order.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is related to Japanese application No.2001-223328 filed on Jul. 24, 2001, whose priority is claimed under 35USC § 119, the disclosure of which is incorporated by reference in itsentirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and amethod for fabricating the same, more specifically, to a semiconductordevice using an insulating film at least in a part of an interlayerdielectric film and a method for fabricating the same, the insulatingfilm has a relative dielectric constant lower than that of siliconnitride and contains an impurity capable of detecting an etching endpoint.

[0004] 2. The Related Art

[0005] With miniaturization and high integration of semiconductordevices, scaling down of internal interconnects and realization ofmultilayer internal interconnects have been proceeding. According withthis, demands for planarization techniques of interlayer dielectricfilms and micro-fabrication such as dry etching have been more severe.Then, to meet these demands, a buried interconnect technique has beenstudied.

[0006] In the buried interconnect technique, a trench for aninterconnect pattern is formed in an interlayer dielectric film, theinside of the trench is buried with an interconnect material, and thenthe interconnect material other than the inside of the trench is removedto leave the interconnect material only inside the trench. Thus, theinterconnect portion is formed in a shape of burying it in theinterlayer dielectric film. Accordingly, it is more advantageous in theplanarization of the interlayer dielectric film than a traditionalmultilevel metallization technique, allowing a copper (Cu) interconnect,which has been difficult in processing by traditional RIE (Reactive IonEtching). The Cu interconnect has low resistance and high reliability,thus attracting attention as a next generation interconnect material.

[0007] In such the buried interconnect technique, an etching stopperfilm is deposited in an interlayer dielectric film in general. Etchingis performed under the condition that a selected ratio is great to thisetching stopper film, whereby a trench and a connection hole for buriedinterconnect are formed in the interlayer dielectric film. As theetching stopper film, a silicon nitride film is used in the case of anSiO₂ based interlayer dielectric film, for example.

[0008] However, the silicon nitride film has a relative dielectricconstant of about seven, significantly greater than that of SiO₂systems, about four, increasing the relative dielectric constant of theentire interlayer dielectric film. Consequently, it is known to generatedefects leading to signal delay or an increase in power consumption.

[0009] Then, Japanese Unexamined Patent Publication No. HEI10(1998)-150105, for example, has been proposed a method of using anorganic low dielectric constant film as an etching stopper film for thepurpose of reducing the capacitance of an interlayer dielectric film,the organic low dielectric constant film has a relative dielectricconstant lower than that of a silicon nitride film and containsfluorine.

[0010] According to this method, as shown in FIG. 3A, an underlayerinsulating film 12 comprised of silicon oxide is deposited as a part ofan interlayer dielectric film on a semiconductor substrate 11 by CVDusing mono-silane and an oxygen gas as source gas. An organic lowdielectric constant film 13 having a relative dielectric constant lowerthan that of silicon nitride is deposited thereon by spin coating, forexample. An insulating film 14 comprised of a silicon oxide film assimilar to the underlayer insulating film 12 and an organic lowdielectric constant film 15 as similar to the organic low dielectricconstant film 13 are deposited thereon.

[0011] Subsequently, a resist film (not shown) is deposited on theorganic low dielectric constant film 15. The resist film is patterned bya photolithography process to form an opening over an area for forming atrench for buried interconnect. The resist film is used as a mask toetch the organic low dielectric constant film 15 as shown in FIG. 3B.Then, the insulating film 14 is etched to form a trench 16 for buriedinterconnect in the organic low dielectric constant film 15 and theinsulating film 14.

[0012] After that, as shown in FIG. 3C, an interconnect layer 17 isformed inside the trench 16 by damascene.

[0013] Subsequently, as shown in FIG. 3D, an insulating film 18comprised of a silicon oxide film as similar to the underlayerinsulating film 12 and the insulating film 14 is deposited over theentire surface of the organic low dielectric constant film 15 and theinterconnect layer 17.

[0014] A resist film (not shown) is deposited on the insulating film 18.The resist film is patterned by the photolithography process to form anopening over an area for forming a connection hole to the interconnectlayer 17. As shown in FIG. 3E, the resist film is used as a mask to etchthe insulating film 18, and a connection hole 19 reaching theinterconnect layer 17 is formed in the insulating film 18.

[0015] Furthermore, as shown in FIG. 3F, a plug 20 comprised oftungsten, for example, is buried inside the connection hole 19.

[0016] After that, an upper interconnect is formed on the insulatingfilm 18 in a pattern of connecting to the plug 20.

[0017] However, as described above, when the organic low dielectricconstant film containing relatively plenty of fluorine is used as theetching stopper film for the purpose of decreasing interlayercapacitance, a problem is arisen that reaction products are generatedgreatly in the bottom of the trench and the connection hole whileetching the interlayer dielectric film and the reaction productsincrease the electric resistance in interconnection.

SUMMARY OF THE INVENTION

[0018] The invention was made in view of the problems. The purpose is toprovide a semiconductor device and a method for fabricating the same,the semiconductor device is capable of reducing interlayer capacitance,terminating etching by controlling endpoint detection highly accurately,not by etching stop utilizing a high selected ratio, and performingetching with fewer reaction products, and has interconnections of lowelectric resistance.

[0019] According to the invention, provided is a semiconductor devicecomprising:

[0020] an underlayer interconnect layer;

[0021] an interlayer dielectric film formed with a connection holereaching the underlayer interconnect layer; and

[0022] an upper interconnect layer buried in the connection hole,

[0023] wherein the interlayer dielectric film includes an insulatingfilm containing an impurity for detecting a first etching end point, afirst insulating film, an insulating film containing an impurity fordetecting a second etching end point and a second insulating film, thesefour films being laminated in this order.

[0024] Additionally, according to the invention, provided is a methodfor fabricating a semiconductor device comprising the steps of:

[0025] forming an insulating film containing an impurity for detecting afirst etching end point, a first insulating film, an insulating filmcontaining an impurity for detecting a second etching end point, and asecond insulating film on an underlayer interconnect layer in thisorder;

[0026] forming a connection hole by etching, the connection holereaching from the surface of the second insulating film to theinsulating film containing the impurity for detecting the first etchingend point;

[0027] forming a protection film in the bottom of the connection hole;

[0028] forming a trench by etching, the trench reaching from the surfaceof the second insulating film to the insulating film containing theimpurity for detecting the second etching end point and connecting withthe connection hole; and

[0029] removing the protection film, and thereafter, burying aconductive material in the connection hole and the trench, therebyforming an upper interconnect layer.

[0030] These and other objects of the present application will becomemore readily apparent from the detailed description given hereinafter.However, it should be understood that the detailed description andspecific examples, while indicating preferred embodiments of theinvention, are given by way of illustration only, since various changesand modifications within the spirit and scope of the invention willbecome apparent to those skilled in the art from this detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIGS. 1A to 1E are schematic sectional views of the processillustrating the fabricating the semiconductor device of the invention

[0032]FIG. 2 is the emission spectra of the spectrometer while theinterlayer dielectric film is being etched.

[0033]FIGS. 3A to 3F are schematic sectional views of the processillustrating the fabricating the semiconductor device of the prior art.

DETAILED DESCRIPTION OF THE INVENTION

[0034] The semiconductor device of the invention mainly has anunderlayer interconnect layer, an interlayer dielectric film, and anupper interconnect layer.

[0035] As the underlayer interconnect layer, any of those being utilizedas the interconnect layer of semiconductor devices is acceptable ingeneral; named are those formed of conductive materials such as animpurity diffused layer, electrodes, and interconnects formed on asemiconductor substrate. More specifically, named are metals such asaluminum, copper, gold, silver, and nickel, or alloys of these; highmelting point metals such as tantalum, titanium, and tungsten, or alloysof these; and a single layer or layered film formed of silicide orpolyside of polysilicon and high melting point metals.

[0036] The interlayer dielectric film deposited over the underlayerinterconnect layer is configured by sequentially laminating at least aninsulating film containing an impurity for detecting a first etching endpoint, a first insulating film, an insulating film containing animpurity for detecting a second etching end point, and a secondinsulating film in this order.

[0037] The insulating film containing the impurity for detecting thefirst etching end point and the insulating film containing the impurityfor detecting the second etching end point are insulating films fordetecting etching end points for the first insulating film and thesecond insulating film, described later, respectively. In considerationof functioning as the interlayer dielectric film, a film having a lowdielectric constant is preferable. Additionally, it dose not necessarilyhave a greater selected ratio to the first insulating film and thesecond insulating film, described later. Materials for these films canbe properly selected according to the method for detecting the etchingend points and the materials for the first and second insulating films,described later. Here, as a method for detecting the etching end pointof the interlayer dielectric film, named is a method of monitoringluminescence intensities in gas during etching.

[0038] For example, impurities contained in the insulating filmcontaining the impurity for detecting the first etching end point andthe insulating film containing the impurity for detecting the secondetching end point are preferably elements not contained in the first andsecond insulating films, described later. For example, phosphorous,arsenic, boron, and fluorine are named. Concentrations of theseimpurities are about 1.0 to 5.0 mol %. Furthermore, the insulating filmscontaining impurities preferably have a dielectric constant of aboutfour or under. More specifically, named are a SiO₂, a SiOF, a SiOC or aCF based film which is formed by a CVD method, and an SOG, HSQ (hydrogensilsesquioxane), an MSQ (methyl silsesquioxane), a PAE (polyaryleneether) or a BCB (benzo cyclobutene) based film which is formed bycoating. The insulating films containing the impurities for detectingthe first and second etching end points are not necessarily the samefilms. Among these, both are preferably a phosphorus silicate glassfilm. The film thickness of these films is not defined particularly, butit is necessary to have a film thickness that is not fully removed eventhough the first and second insulating films, described later, are overetched. More specifically, it is preferably about 10 to 50 nm.

[0039] The first and second insulating films are not definedparticularly when they are materials configuring interlayer dielectricfilms in general. For example, those similar to the insulating filmsdescribed above are named. Among these, a silicon oxide film ispreferable. The film thickness of these insulating films is not definedparticularly; they are preferably adjusted about 500 to 2000 nm as theentire interlayer dielectric films.

[0040] It is acceptable that the upper interconnect layer is any ofthese being utilized as interconnect layers for semiconductor devices ingeneral. It can be formed of materials similar to those exemplified asthe underlayer interconnect layer. Additionally, the upper interconnectlayer is formed as being buried in the trench formed in the surface ofthe interlayer dielectric film. Preferably, the top surfaces of theinterlayer dielectric film and the upper interconnect layer are matched.Furthermore, generally, the connection hole reaching the underlayerinterconnect layer is formed inside the trench buried with the upperinterconnect layer. The upper interconnect layer may be buried into theconnection hole, or the upper interconnect layer may be formed so as tobe connected to a contact plug, the contact plug is formed in theconnection hole separately from the upper interconnect layer. Moreover,the contact plug can be formed of a single layer or layered film ofconductive materials generally used for connecting interconnect layers.

[0041] Besides, in the method for fabricating the semiconductor deviceof the invention, first, the insulating film containing the impurity fordetecting the first etching end point, the first insulating film, theinsulating film containing the impurity for detecting the second etchingend point, and the second insulating film are sequentially deposited onthe underlayer interconnect layer in this order. These insulating filmscan be deposited by selecting various publicly known methods such assputtering, vacuum deposition, the electron beam process, CVD, plasmaCVD, spin coating, the doctor blade process, and the sol-gel process.Additionally, in the insulating films containing impurities, impuritiescan be introduced by ion injection, solid phase diffusion or vapor phasediffusion after the insulating film is deposited, or impurities can beintroduced into raw materials of the insulating film to deposit theinsulating film containing the impurities.

[0042] Then, the connection hole reaching from the surface of the secondinsulating film to the insulating film containing the impurity fordetecting the first etching end point is formed by etching. For etchingin this case, various etching methods are named such as wet etching ordry etching, but dry etching is preferable. Etching is terminated whenat least the second insulating film, the insulating film containing theimpurity for detecting the second etching end point and the firstinsulating film are fully penetrated and etching for the insulating filmcontaining the impurity for detecting the first etching end point isconfirmed. The confirmation of etching for the insulating filmcontaining the impurity for detecting the first etching end point can beperformed surely and simply by performing monitoring as described aboveand detection of the impurity for detecting the first etching end point.

[0043] Subsequently, a protection film is formed in the bottom of theconnection hole. Kinds of the protection film here are not definedparticularly, but an organic protection film is appropriate inconsideration of forming the protection film only in the bottom of theconnection hole and removal of the protection film. It is acceptablethat the protection film is formed over the entire surface of theinterlayer dielectric film including the connection hole and theprotection film formed in the area other than the bottom of theconnection hole is removed by etching or lift-off, or that it is formedonly in the bottom of the connection hole by spin coating. The filmthickness of the protection film is not defined particularly. It can beadjusted properly by materials for each layer configuring the interlayerdielectric film and etching conditions.

[0044] Then, the trench is formed by etching, the trench reaches fromthe surface of the second insulating film to the insulating filmcontaining the impurity for detecting the second etching end point andconnects with the connection hole. The formation of the trench here canbe performed as similar to the formation of the connection holedescribed above. In addition, either of the connection hole and thetrench may be formed beforehand; when the trench is formed beforehand,it is appropriate that the connection hole is formed so as to be placedinside the trench. Furthermore, when the trench is formed beforehand,the protection film is preferably formed in the bottom of the trench,not in the bottom of the connection hole.

[0045] Moreover, after this process, the protection film formed in thebottom of the connection hole (or the bottom of the trench) and theinsulating films containing the impurities for detecting the first andsecond etching end points are preferably almost fully removed before thesubsequent process where a conductive material is buried in theconnection hole and the trench. These films can be removed by selectingproper conditions according to wet etching and dry etching.

[0046] Besides, the conductive material is buried in the connection holeand the trench. For the conductive material here, the material filmsexemplified in the above-described upper interconnect layer are named.The conductive material can be buried by depositing a conductivematerial film over the entire surface of the second insulating film toetch back the conductive material film until the surface of the secondinsulating film is exposed. Etch back can be performed by CMP, forexample. Additionally, it is acceptable that the connection hole and thetrench are buried with the same material film by the same process, orthat the connection hole is first buried with the conductive materialfilm and the trench is further buried with the same or differentconductive material film.

[0047] Hereafter, the semiconductor device of the invention and themethod for fabricating the same will be described with reference to thedrawings.

[0048] First, as shown in FIG. 1A, a phosphorus silicate glass filmcontaining phosphorus (PSG film having a relative dielectric constant ofabout four), for example, is deposited about 10 to 50 nm in filmthickness on an interconnect layer 1 formed on a semiconductor substrateas an insulating film 2 a for detecting a first etching end point. Asilicon oxide film (P-tetraethoxysilane (TEOS) film) by plasmadeposition using a TEOS gas and an O₂ gas as raw material is depositedabout 250 to 750 nm in film thickness thereon as an insulating film 2. APSG film as similar to the insulating film 2 a is deposited about 10 to50 nm in film thickness further thereon as an insulating film 3 a fordetecting a second etching end point. A P-TEOS film as similar to theinsulating film 2 is deposited about 250 to 750 nm in film thicknessthereon as an insulating film 3. A resist pattern 4 for forming aconnection hole is formed thereon by a photolithography process.

[0049] Subsequently, as shown in FIG. 1B, the resist pattern 4 is usedas a mask to form a connection hole 5 by etching. Etching at this timeis performed where source power/bias power is 2170W/1800W, pressure is20 mTorrs, and a C₅F₈ gas, Ar gas and O₂ gas are used as etching gas.Furthermore, during etching, a spectrometer is used to monitorluminescence intensities of plasma gas, and termination of etching isdetermined by detecting changes in the luminescence intensities of thespectrometer corresponding to the period of time while the insulatingfilm 2 a for detecting the first etching end point is being etched inthe stage nearly finishing etching.

[0050] More specifically, as shown in FIG. 2, the emission spectra ofthe spectrometer while the insulating film 2 a for detecting the firstetching end point is being etched, the insulating film 2 a is formed ofthe PSG film, shows that the luminescence intensity is great near awavelength of about 253 nm as compared with the period of time whileetching the insulating film 2 formed of the P-TEOS film. This is awavelength of a chemical/electron pair of phosphorus contained in thePSG film. According to the emission spectra at this wavelength, thetermination of etching can be determined.

[0051] Subsequently, the resist pattern 4 is removed by ashing.

[0052] Then, as shown in FIG. 1C, an organic based bottomanti-reflective coating (BARC) 6 is deposited in the bottom of theconnection hole by spin coating at a rotation of about 1000 to 4000 rpm.After that, a resist is coated over the entire surface of thesemiconductor substrate obtained, and a resist pattern 7 for formingtrench interconnect is formed by a photolithography process.

[0053] The organic based bottom anti-reflective coating 6 in the bottomof the connection hole 5 was formed in order not to etch theinterconnect layer 1 due to the bottom of the connection hole 5 beingetched during etching in the subsequent process.

[0054] Then, as shown in FIG. 1D, the resist pattern 7 for forming thetrench interconnect is used as a mask to form a trench 8. The trench 8is formed in which etching is performed while luminescence intensitiesof the spectrometer is being monitored and changes in the luminescenceintensities of the spectrometer corresponding to the period of timewhile the insulating film 3 a for detecting the second etching end pointis being etched are detected to terminate etching, as described above.

[0055] Subsequently, as shown in FIG. 1E, the resist pattern 7 and theorganic bottom anti-reflective coating 6 in the bottom of the connectionhole 5 are removed by ashing. Furthermore, the insulating film 2 a fordetecting the first etching end point and the insulating film 3 a fordetecting the second etching end point are removed by etching.

[0056] After that, conductive materials are buried in the connectionhole 5 and the trench 8 by a publicly known method, and the formation ofthe trench interconnect part is completed.

[0057] In this manner, the PSG film is interposed in the interlayerdielectric film, whereby the detection of the etching end point can beperformed surely.

[0058] According to the invention, the interlayer dielectric film isconfigured by sequentially laminating the insulating film containing theimpurity for detecting the first etching end point, the first insulatingfilm, the insulating film containing the impurity for detecting thesecond etching end point, and the second insulating film in this order.Therefore, the realization of a lower dielectric constant in theinterlayer dielectric film which is a problem in the scaled downsemiconductor devices can be attained without using a silicon nitridefilm having a higher dielectric constant generally used as the etchingstopper for the first and second insulating films. A semiconductordevice intending the reduction in capacitance of the interlayerdielectric film and preventing signal delay or an increase in powerconsumption can be obtained.

[0059] In addition, according to the invention, etching can beterminated by detecting the impurities contained in the insulatingfilms, not by etching stop based on the difference in a selected ratioin etching the first and second insulating films. Thus, the etching endpoint can be determined easily, simply, surely and highly accurately,avoiding excessive over etching. Also, performing such the determinationof the etching end point leads to allowing the prevention of reactionproducts from being left in the connection hole or trench, the reactionproducts are generated during etching, and allowing the avoidance of anincrease in electric resistance and connection failure caused by thereaction products. A semiconductor device having high reliability can befabricated as an improvement in yields and a reduction in fabricationcosts are intended.

What is claimed is:
 1. A semiconductor device comprising: an underlayerinterconnect layer; an interlayer dielectric film formed with aconnection hole reaching the underlayer interconnect layer; and an upperinterconnect layer buried in the connection hole, wherein the interlayerdielectric film includes an insulating film containing an impurity fordetecting a first etching end point, a first insulating film, aninsulating film containing an impurity for detecting a second etchingend point and a second insulating film, these four films being laminatedin this order.
 2. A semiconductor device according to claim 1, whereinthe first insulating film and the second insulating film are formed ofsilicon oxide.
 3. A semiconductor device according to claim 1, whereinthe insulating film containing the impurity for detecting the firstetching end point and the insulating film containing the impurity fordetecting the second etching end point contain phosphorus, arsenic,boron or fluorine as the impurities.
 4. A semiconductor device accordingto claim 1, wherein the impurities are contained in a concentration of 1to 5 mol %.
 5. A semiconductor device according to claim 1, wherein theinsulating film containing the impurity for detecting the first etchingend point and the insulating film containing the impurity for detectingthe second etching end point have a dielectric constant of 4 or less. 6.A semiconductor device according to claim 1, wherein the insulating filmcontaining the impurity for detecting the first etching end point andthe insulating film containing the impurity for detecting the secondetching end point are selected from a SiO₂, a SiOF, a SiOC or a CF basedfilm which is formed by a CVD method, and an SOG, HSQ (hydrogensilsesquioxane), an MSQ (methyl silsesquioxane), a PAE (polyaryleneether) or a BCB (benzo cyclobutene) based film which is formed bycoating.
 7. A semiconductor device according to claim 1, wherein theinsulating film containing the impurity for detecting the first etchingend point and the insulating film containing the impurity for detectingthe second etching end point have a thickness of 10 to 50 μm.
 8. Asemiconductor device according to claim 1, wherein the interlayerdielectric film has a thickness of 500 to 2,000 nm.
 9. A semiconductordevice according to claim 1, wherein the insulating film containing theimpurity for detecting the first etching end point and the insulatingfilm containing the impurity for detecting the second etching end pointare formed of phosphorus silicate glass.
 10. A method for fabricating asemiconductor device comprising the steps of: forming an insulating filmcontaining an impurity for detecting a first etching end point, a firstinsulating film, an insulating film containing an impurity for detectinga second etching end point, and a second insulating film on anunderlayer interconnect layer in this order; forming a connection holeby etching, the connection hole reaching from the surface of the secondinsulating film to the insulating film containing the impurity fordetecting the first etching end point; forming a protection film in thebottom of the connection hole; forming a trench by etching, the trenchreaching from the surface of the second insulating film to theinsulating film containing the impurity for detecting the second etchingend point and connecting with the connection hole; and removing theprotection film, and thereafter, burying a conductive material in theconnection hole and the trench, thereby forming an upper interconnectlayer.